Comparator

ABSTRACT

A semiconductor device includes a selection signal generation circuit configured to generate a selection signal by comparing a first input signal and a second input signal. The semiconductor device also includes a comparison signal generation circuit configured to output a comparison signal by selecting one of the first input signal and the second input signal based on the selection signal.

CROSS-REFERENCE TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. § 119(a) toKorean Patent Application No. 10-2020-0007895, filed on Jan. 21, 2020,in the Korean Intellectual Property Office, the disclosure of which isincorporated herein by reference in its entirety.

BACKGROUND 1. Technical Field

Embodiments of the disclosure may generally relate to a comparator whichoperates at a high speed.

2. Related Art

An electronic device including a semiconductor device may performvarious internal operations. Whether to perform the internal operationsmay be determined through a comparator which compares the magnitudes ofsignals. As the operation of the comparator becomes faster, the speed ofthe internal operations is improved, which may help the high speedoperation of the electronic device.

SUMMARY

In an embodiment, a semiconductor device may include a selection signalgeneration circuit configured to generate a selection signal bycomparing a first input signal and a second input signal. Thesemiconductor device may also include a comparison signal generationcircuit configured to output a comparison signal by selecting one of thefirst input signal and the second input signal based on the selectionsignal.

In an embodiment, a semiconductor device may include a selection signalgeneration circuit configured to generate an (N−1){circumflex over( )}th bit of a selection signal which has a first logic level, when anN{circumflex over ( )}th bit of a first input signal is different froman N{circumflex over ( )}th bit of a second input signal. Thesemiconductor device may also include a comparison signal generationcircuit configured to output the N{circumflex over ( )}th bit of thefirst input signal as a comparison signal when the (N−1){circumflex over( )}th bit of the selection signal has the first logic level, wherein Nis a natural number of 2 or more.

In an embodiment, a semiconductor device may include a selection signalgeneration circuit configured to generate an (N−1){circumflex over( )}th bit of a selection signal which has a first logic level, when anN{circumflex over ( )}th bit of a first input signal is different froman N{circumflex over ( )}th bit of a second input signal. Thesemiconductor device may also include a comparison signal generationcircuit configured to output a comparison signal by inverting andbuffering the N{circumflex over ( )}th bit of the second input signalwhen the (N−1){circumflex over ( )}th bit of the selection signal hasthe first logic level, wherein N is a natural number of 2 or more.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram illustrating a configuration of a comparatorin accordance with an embodiment of the disclosure.

FIG. 2 is a circuit diagram illustrating a selection signal generationcircuit included in the comparator illustrated in FIG. 1.

FIG. 3 is a circuit diagram illustrating a comparison signal generationcircuit included in the comparator illustrated in FIG. 1.

FIGS. 4 and 5 are circuit diagrams to assist in the explanation of theoperation of the comparison signal generation circuit illustrated inFIG. 3.

FIG. 6 is a circuit diagram illustrating another embodiment of thecomparison signal generation circuit included in the comparatorillustrated in FIG. 1.

FIGS. 7 and 8 are circuit diagrams to assist in the explanation of theoperation of the comparison signal generation circuit illustrated inFIG. 6.

DETAILED DESCRIPTION

The term “preset” means that the numerical value of a parameter ispredetermined when the parameter is used in a process or algorithm.Depending on an embodiment, the numerical value of a parameter may beset when a process or algorithm starts or may be set during a periodduring which the process or algorithm is executed.

Terms such as “first” and “second” used to distinguish variouscomponents are not limited by components. For example, a first componentmay be named as a second component, and conversely, the second componentmay be named as the first component.

When it is described that one component is “coupled” or “connected” toanother component, it is to be understood that the one component may becoupled or connected the other component either directly or through anintermediary component. On the other hand, the descriptions of “directlycoupled” and “directly connected” should be understood to mean that theone component is coupled and connected to the other component directlywithout the intervention of another component.

“Logic high level” and “logic low level” are used to describe logiclevels of signals. A signal having a “logic high level” is distinguishedfrom a signal having a “logic low level.” For example, when a signalhaving a first voltage corresponds to a “logic high level,” a signalhaving a second voltage may correspond to a “logic low level.” Dependingon an embodiment, a “logic high level” may be set to a voltage higherthan a “logic low level.” Meanwhile, depending on an embodiment, logiclevels of signals may be set to different logic levels or opposite logiclevels. For example, depending on an embodiment, a signal having a logichigh level may be set to have a logic low level, and a signal having alogic low level may be set to have a logic high level.

Hereinafter, various examples of embodiments of the disclosure will bedescribed in detail with reference to the accompanying drawings. Theseembodiments are only for illustrating the disclosure, and the scope ofprotection of the disclosure is not limited by these embodiments.

Various embodiments of the present disclosure are directed to acomparator which operates at a high speed. According to someembodiments, through selecting one bit among bits included in inputsignals, based on selection signals generated by comparing therespective bits included in the input signals, and generating acomparison signal by the selected bit of an input signal, the area andcurrent consumption of a circuit which performs the operation ofcomparing the input signals may be reduced.

FIG. 1 is a block diagram illustrating a comparator 10 in accordancewith an embodiment of the present disclosure. As illustrated in FIG. 1,the comparator 10 may include a selection signal generation circuit 100and a comparison signal generation circuit 110.

The selection signal generation circuit 100 may generate a selectionsignal SEL<L−1:1> based on a first input signal IN1<L:2> and a secondinput signal IN2<L:2>, The selection signal generation circuit 100 maycompare a second bit IN1<2> of the first input signal and a second bitIN2<2> of the second input signal, and thereby, may generate a first bitSEL<1> of the selection signal which has a preset logic level determineddepending on a comparison result. The selection signal generationcircuit 100 may generate the first bit SEL<1> of the selection signalwhich has a first logic level, when the second bit IN1<2> of the firstinput signal is different from the second bit IN2<2> of the second inputsignal, and may generate the first bit SEL<1> of the selection signalwhich has a second logic level, when the second bit IN1<2> of the firstinput signal is the same as the second bit IN2<2> of the second inputsignal. In the present embodiment, the first logic level may be set to alogic low level and the second logic level may be set to a logic highlevel, but it is to be noted that the embodiment is not limited thereto.The selection signal generation circuit 100 may compare an L{circumflexover ( )}th bit IN1<L> of the first input signal and an L{circumflexover ( )}th bit IN2<L> of the second input signal, and thereby, maygenerate an (L−1){circumflex over ( )}th bit SEL<L−1> of the selectionsignal which has a preset logic level determined depending on acomparison result. In the present embodiment, the selection signalgeneration circuit 100 generates the selection signal SEL<L−1:1> byusing the first input signal IN1<L:2> and the second input signalIN2<L:2>, but bits of input signals, which are used to generate theselection signal SEL<L−1:1>, are not limited thereto.

The comparison signal generation circuit 110 may generate a comparisonsignal COM from the first input signal IN1<L:1> or the second inputsignal IN2<L:1> based on the selection signal SEL<L−1:1>. When the(L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal whichhas the first logic level is inputted, the comparison signal generationcircuit 110 may output the L{circumflex over ( )}th bit IN1<L> of thefirst input signal as the comparison signal COM or output the comparisonsignal COM by inverting and buffering the L{circumflex over ( )}th bitIN2<L> of the second input signal. When the (L−1){circumflex over ( )}thbit SEL<L−1> of the selection signal which has the second logic level isinputted and an (L−2){circumflex over ( )}th bit SEL<L−2> of theselection signal which has the first logic level is inputted, thecomparison signal generation circuit 110 may output an (L−1){circumflexover ( )}th bit IN1<L−1> of the first input signal as the comparisonsignal COM or output the comparison signal COM by inverting andbuffering an (L−1){circumflex over ( )}th bit IN2<L−1> of the secondinput signal. When (L−1){circumflex over ( )}th and (L−2){circumflexover ( )}th bits SEL<L−1:L−2> of the selection signal which have thesecond logic level are inputted and an (L−3){circumflex over ( )}th bitSEL<L−3> of the selection signal which has the first logic level isinputted, the comparison signal generation circuit 110 may output an(L−2){circumflex over ( )}th bit IN1<L−2> of the first input signal asthe comparison signal COM or output the comparison signal COM byinverting and buffering an (L−2){circumflex over ( )}th bit IN2<L−2> ofthe second input signal. When (L−1){circumflex over ( )}th to secondbits SEL<L−1:2> of the selection signal which have the second logiclevel are inputted and the first bit SEL<1> of the selection signalwhich has the first logic level is inputted, the comparison signalgeneration circuit 110 may output the second bit IN1<2> of the firstinput signal as the comparison signal COM or output the comparisonsignal COM by inverting and buffering the second bit IN2<2> of thesecond input signal. When the (L−1){circumflex over ( )}th to first bitsSEL<L−1:1> of the selection signal which have the second logic level areinputted, the comparison signal generation circuit 110 may output thecomparison signal COM by buffering a first bit IN1<1> of the first inputsignal or output the comparison signal COM by inverting and buffering afirst bit IN2<1> of the second input signal. A logic level of thecomparison signal COM may include information on a comparison result ofthe first input signal IN1<L:1> and the second input signal IN2<L:1>.For example, when the comparison signal COM has the first logic level,it may mean that the first input signal IN1<L:1> is set to be equal toor smaller than the second input signal IN2<L:1>, and when thecomparison signal COM has the second logic level, it may mean that thefirst input signal IN1<L:1> is set to be larger than the second inputsignal IN2<L:1>. In the present embodiment, the first logic level may beset to a logic low level and the second logic level may be set to alogic high level, but it is to be noted that the embodiment is notlimited thereto.

FIG. 2 is a circuit diagram illustrating the selection signal generationcircuit 100 included in the comparator 10. As illustrated in FIG. 2, theselection signal generation circuit 100 may include first to(L−1){circumflex over ( )}th XNOR gates XNOR(1:L−1). The first XNOR gateXNOR(1) may receive the second bit IN1<2> of the first input signal andthe second bit IN2<2> of the second input signal, perform an XNOR logicoperation, and generate the first bit SEL<1> of the selection signal.The first XNOR gate XNOR(1) may generate the first bit SEL<1> of theselection signal which has a logic low level, when the second bit IN1<2>of the first input signal and the second bit IN2<2> of the second inputsignal have different logic levels. The first XNOR gate XNOR(1) maygenerate the first bit SEL<1> of the selection signal which has a logichigh level, when the second bit IN1<2> of the first input signal and thesecond bit IN2<2> of the second input signal have the same logic level.The second XNOR gate XNOR(2) may receive a third bit IN1<3> of the firstinput signal and a third bit IN2<3> of the second input signal, performan XNOR logic operation, and generate the second bit SEL<2> of theselection signal. The second XNOR gate XNOR(2) may generate the secondbit SEL<2> of the selection signal which has a logic low level, when thethird bit IN1<3> of the first input signal and the third bit IN2<3> ofthe second input signal have different logic levels. The second XNORgate XNOR(2) may generate the second bit SEL<2> of the selection signalwhich has a logic high level, when the third bit IN1<3> of the firstinput signal and the third bit IN2<3> of the second input signal havethe same logic level. The (L−1){circumflex over ( )}th XNOR gateXNOR(L−1) may receive the L{circumflex over ( )}th bit IN1<L> of thefirst input signal and the L″th bit IN2<L> of the second input signal,perform an XNOR logic operation, and generate the (L−1){circumflex over( )}th bit SEL<L−1> of the selection signal. The (L−1){circumflex over( )}th XNOR gate XNOR(L−1) may generate the (L−1){circumflex over ( )}thbit SEL<L−1> of the selection signal which has a logic low level, whenthe L″th bit IN1<L> of the first input signal and the L{circumflex over( )}th bit IN2<L> of the second input signal have different logiclevels. The (L−1){circumflex over ( )}th XNOR gate XNOR(L−1) maygenerate the (L−1){circumflex over ( )}th bit SEL<L−1> of the selectionsignal which has a logic high level, when the L{circumflex over ( )}thbit IN1<L> of the first input signal and the L″th bit IN2<L> of thesecond input signal have the same logic level.

FIG. 3 is a circuit diagram illustrating the comparison signalgeneration circuit 110 included in the comparator 10. As illustrated inFIG. 3, a comparison signal generation circuit 110 a may include aninput signal reception circuit 31 and first to (L−1){circumflex over( )}th code selection circuits M3(L−1:1).

The input signal reception circuit 31 may include inverters IV31 andIV32 and a NAND gate NAND31 which are electrically coupled. The inverterIV31 may invert and buffer the first bit IN2<1> of the second inputsignal, and may output an output signal. The NAND gate NAND31 and theinverter IV32 may receive the first bit IN1<1> of the first input signaland the output signal of the inverter IV31, perform an AND logicoperation, and generate a first pre-code PC<1>.

The first code selection circuit M3(1) may output a second pre-codePC<2> by selecting the second bit IN1<2> of the first input signal orthe first pre-code PC<1> based on the first bit SEL<1> of the selectionsignal. The first code selection circuit M3(1) may output the second bitIN1<2> of the first input signal as the second pre-code PC<2> when thefirst bit SEL<1> of the selection signal has a logic low level. Thefirst code selection circuit M3(1) may output the first pre-code PC<1>as the second pre-code PC<2> when the first bit SEL<1> of the selectionsignal has a logic high level.

The second code selection circuit M3(2) may output a third pre-codePC<3> by selecting the third bit IN1<3> of the first input signal or thesecond pre-code PC<2> based on the second bit SEL<2> of the selectionsignal. The second code selection circuit M3(2) may output the third bitIN1<3> of the first input signal as the third pre-code PC<3> when thesecond bit SEL<2> of the selection signal has a logic low level. Thesecond code selection circuit M3(2) may output the second pre-code PC<2>as the third pre-code PC<3> when the second bit SEL<2> of the selectionsignal has a logic high level.

The (L−2){circumflex over ( )}th code selection circuit M3(L−2) mayoutput an (L−1){circumflex over ( )}th pre-code PC<L−1> by selecting the(L−1){circumflex over ( )}th bit IN1<L−1> of the first input signal oran (L−2){circumflex over ( )}th pre-code PC<L−2> based on the(L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal. The(L−2){circumflex over ( )}th code selection circuit M3(L−2) may outputthe (L−1){circumflex over ( )}th bit IN1<L−1> of the first input signalas the (L−1){circumflex over ( )}th pre-code PC<L−1> when the(L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal has alogic low level. The (L−2){circumflex over ( )}th code selection circuitM3(L−2) may output the (L−2)″th pre-code PC<L−2> as the (L−1){circumflexover ( )}th pre-code PC<L−1> when the (L−2){circumflex over ( )}th bitSEL<L−2> of the selection signal has a logic high level.

The (L−1){circumflex over ( )}th code selection circuit M3(L−1) mayoutput the comparison signal COM by selecting the L″th bit IN1<L> of thefirst input signal or the (L−1){circumflex over ( )}th pre-code PC<L−1>based on the (L−1){circumflex over ( )}th bit SEL<L−1> of the selectionsignal. The (L−1){circumflex over ( )}th code selection circuit M3(L−1)may output the L{circumflex over ( )}th bit IN1<L> of the first inputsignal as the comparison signal COM when the (L−1){circumflex over( )}th bit SEL<L−1> of the selection signal has a logic low level. The(L−1){circumflex over ( )}th code selection circuit M3(L−1) may outputthe (L−1){circumflex over ( )}th pre-code PC<L−1> as the comparisonsignal COM when the (L−1){circumflex over ( )}th bit SEL<L−1> of theselection signal has a logic high level.

FIGS. 4 and 5 are circuit diagrams to assist in the explanation of theoperation of the comparison signal generation circuit 110 a.

As illustrated in FIG. 4, the operation of the comparison signalgeneration circuit 110 a when a first input signal IN1<5:1> is a binary‘10100’ (a decimal number ‘20’) and a second input signal IN2<5:1> is abinary ‘01110’ (a decimal number ‘14’) is as follows. Here, ‘0’ may meana logic low level, and ‘1’ may mean a logic high level. Because a fifthbit IN1<5> of the first input signal and a fifth bit IN2<5> of thesecond input signal are different from each other, a fourth bit SEL<4>of a selection signal is generated at a logic low level, and thecomparison signal COM is generated at a logic high level as a logiclevel of the fifth bit IN1<5> of the first input signal. It may beconfirmed that, when the comparison signal COM is the logic high level,the first input signal IN1<5:1> is set to be larger than the secondinput signal IN2<5:1>. The comparison signal generation circuit 110 aaccording to the present embodiment may generate the comparison signalCOM from the fifth bit IN1<5> of the first input signal by using thefourth bit SEL<4> of the selection signal which is generated bycomparing only most significant bits of the first input signal IN1<5:1>and the second input signal IN2<5:1>. Because the comparison signalgeneration circuit 110 a according to the present embodiment is realizedto be capable of performing a comparison operation based only oncomparison of some bits included in the first input signal IN1<5:1> andthe second input signal IN2<5:1>, an area and current consumption may bereduced or minimized.

As illustrated in FIG. 5, the operation of the comparison signalgeneration circuit 110 a when a first input signal IN1<5:1> is a binary‘10110’ (a decimal number ‘22’) and a second input signal IN2<5:1> is abinary ‘11001’ (a decimal number ‘25’) is as follows. Because a fifthbit IN1<5> of the first input signal and a fifth bit IN2<5> of thesecond input signal are the same as each other, a fourth bit SEL<4> of aselection signal is generated at a logic high level, and because afourth bit IN1<4> of the first input signal and a fourth bit IN2<4> ofthe second input signal are different from each other, a third bitSEL<3> of the selection signal is generated at a logic low level. Thecomparison signal COM is generated at a logic low level as a logic levelof the fourth bit IN1<4> of the first input signal by the third bitSEL<3> of the selection signal. It may be confirmed that, when thecomparison signal COM has a logic low level, the first input signalIN1<5:1> is set to be equal to or smaller than the second input signalIN2<5:1>. The comparison signal generation circuit 110 a according tothe present embodiment may generate the comparison signal COM from thefourth bit IN1<4> of the first input signal by using the fourth andthird bits SEL<4:3> of the selection signal which are generated bysequentially comparing most significant bits of the first input signalIN1<5:1> and the second input signal IN2<5:1>. Because the comparisonsignal generation circuit 110 a according to the present embodiment isrealized to be capable of performing a comparison operation based onlyon comparison of some bits included in the first input signal IN1<5:1>and the second input signal IN2<5:1>, an area and current consumptionmay be reduced or minimized.

FIG. 6 is a circuit diagram illustrating another embodiment of thecomparison signal generation circuit 110 included in the comparator 10.As illustrated in FIG. 6, a comparison signal generation circuit 110 bmay include an input signal reception circuit 41, first to(L−1){circumflex over ( )}th code selection circuits M4(L−1:1), and aninverter IV43.

The input signal reception circuit 41 may include inverters IV41 andIV42 and a NAND gate NAND41 which are electrically coupled. The inverterIV41 may invert and buffer the first bit IN2<1> of the second inputsignal, and may output an output signal. The NAND gate NAND41 and theinverter IV42 may receive the first bit IN1<1> of the first input signaland the output signal of the inverter IV41, perform an AND logicoperation, and generate a first pre-code PC<1>.

The first code selection circuit M4(1) may output a second pre-codePC<2> by selecting the second bit IN2<2> of the second input signal orthe first pre-code PC<1> based on the first bit SEL<1> of the selectionsignal. The first code selection circuit M4(1) may output the second bitIN2<2> of the second input signal as the second pre-code PC<2> when thefirst bit SEL<1> of the selection signal has a logic low level. Thefirst code selection circuit M4(1) may output the first pre-code PC<1>as the second pre-code PC<2> when the first bit SEL<1> of the selectionsignal has a logic high level.

The second code selection circuit M4(2) may output a third pre-codePC<3> by selecting the third bit IN2<3> of the second input signal orthe second pre-code PC<2> based on the second bit SEL<2> of theselection signal. The second code selection circuit M4(2) may output thethird bit IN2<3> of the second input signal as the third pre-code PC<3>when the second bit SEL<2> of the selection signal has a logic lowlevel. The second code selection circuit M4(2) may output the secondpre-code PC<2> as the third pre-code PC<3> when the second bit SEL<2> ofthe selection signal has a logic high level.

The (L−2){circumflex over ( )}th code selection circuit M4(L−2) mayoutput an (L−1){circumflex over ( )}th pre-code PC<L−1> by selecting the(L−1){circumflex over ( )}th bit IN2<L−1> of the second input signal oran (L−2){circumflex over ( )}th pre-code PC<L−2> based on the(L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal. The(L−2){circumflex over ( )}th code selection circuit M4(L−2) may outputthe (L−1){circumflex over ( )}th bit IN2<L−1> of the second input signalas the (L−1){circumflex over ( )}th pre-code PC<L−1> when the(L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal has alogic low level. The (L−2){circumflex over ( )}th code selection circuitM4(L−2) may output the (L−2){circumflex over ( )}th pre-code PC<L−2> asthe (L−1){circumflex over ( )}th pre-code PC<L−1> when the(L−2){circumflex over ( )}th bit SEL<L−2> of the selection signal has alogic high level.

The (L−1){circumflex over ( )}th code selection circuit M4(L−1) mayoutput the comparison signal COM by selecting the L{circumflex over( )}th bit IN2<L> of the second input signal or the (L−1){circumflexover ( )}th pre-code PC<L−1> based on the (L−1){circumflex over ( )}thbit SEL<L−1> of the selection signal. The (L−1){circumflex over ( )}thcode selection circuit M4(L−1) may select and output the L{circumflexover ( )}th bit IN2<L> of the second input signal when the(L−1){circumflex over ( )}th bit SEL<L−1> of the selection signal has alogic low level. The (L−1){circumflex over ( )}th code selection circuitM4(L−1) may select and output the (L−1){circumflex over ( )}th pre-codePC<L−1> when the (L−1){circumflex over ( )}th bit SEL<L−1> of theselection signal has a logic high level. The inverter IV43 may outputthe comparison signal COM by inverting and buffering the output signalof the (L−1){circumflex over ( )}th code selection circuit M4(L−1).

FIGS. 7 and 8 are circuit diagrams to assist in the explanation of theoperation of the comparison signal generation circuit 110 b.

As illustrated in FIG. 7, the operation of the comparison signalgeneration circuit 110 b when a first input signal IN1<5:1> is a binary‘10100’ (a decimal number ‘20’) and a second input signal IN2<5:1> is abinary ‘01110’ (a decimal number ‘14’) is as follows. Because a fifthbit IN1<5> of the first input signal and a fifth bit IN2<5> of thesecond input signal are different from each other, a fourth bit SEL<4>of a selection signal is generated at a logic low level, and thecomparison signal COM is generated at a logic high level by invertingand buffering a logic level of the fifth bit IN2<5> of the second inputsignal. It may be confirmed that, when the comparison signal COM has alogic high level, the first input signal IN1<5:1> is set to be largerthan the second input signal IN2<5:1>. The comparison signal generationcircuit 110 b according to the present embodiment may generate thecomparison signal COM from the fifth bit IN2<5> of the second inputsignal by using the fourth bit SEL<4> of the selection signal which isgenerated by comparing only most significant bits of the first inputsignal IN1<5:1> and the second input signal IN2<5:1>. Because thecomparison signal generation circuit 110 b according to the presentembodiment is realized to be capable of performing a comparisonoperation based only on comparison of some bits included in the firstinput signal IN1<5:1> and the second input signal IN2<5:1>, an area andcurrent consumption may be reduced or minimized.

As illustrated in FIG. 8, the operation of the comparison signalgeneration circuit 110 b when a first input signal IN1<5:1> is a binary‘10110’ (a decimal number ‘22’) and a second input signal IN2<5:1> is abinary ‘11001’ (a decimal number ‘25’) is as follows. Because a fifthbit IN1<5> of the first input signal and a fifth bit IN2<5> of thesecond input signal are the same as each other, a fourth bit SEL<4> of aselection signal is generated at a logic high level, and because afourth bit IN1<4> of the first input signal and a fourth bit IN2<4> ofthe second input signal are different from each other, a third bitSEL<3> of the selection signal is generated at a logic low level. Thecomparison signal COM is generated at a logic low level by inverting andbuffering a logic level of the fourth bit IN2<4> of the second inputsignal by the third bit SEL<3> of the selection signal. It may beconfirmed that, when the comparison signal COM has a logic low level,the first input signal IN1<5:1> is set to be equal to or smaller thanthe second input signal IN2<5:1>. The comparison signal generationcircuit 110 b according to the present embodiment may generate thecomparison signal COM from the fourth bit IN2<4> of the second inputsignal by using the fourth and third bits SEL<4:3> of the selectionsignal which are generated by sequentially comparing most significantbits of the first input signal IN1<5:1> and the second input signalIN2<5:1>. Because the comparison signal generation circuit 110 baccording to the present embodiment is realized to be capable ofperforming a comparison operation based only on comparison of some bitsincluded in the first input signal IN1<5:1> and the second input signalIN2<5:1>, an area and current consumption may be reduced or minimized.

While various embodiments have been described above, it will beunderstood by those skilled in the art that the described embodimentsrepresent only a limited number of possible examples. Accordingly, thecomparator described herein should not be limited to based on thedescribed embodiments.

What is claimed is:
 1. A semiconductor device comprising: a selectionsignal generation circuit configured to generate a selection signal bycomparing a first input signal and a second input signal; and acomparison signal generation circuit configured to output a comparisonsignal by selecting one of the first input signal and the second inputsignal responsive to the selection signal, the comparison signalgeneration circuit comprising a plurality of serially-connected codeselection circuits, each code selection circuit having: first and secondinput signal ports, a selection signal port and an output port fromwhich the comparison signal is output responsive to a signal provided tothe selection signal port; wherein a logic level of the comparisonsignal output from each serially-connected code selection circuit is setresponsive to a comparison of a first signal input to the first signalinput port to a second input to the second signal input port; whereinthe comparison signal has a first logic level when the first signalinput to the first signal input port is equal to or smaller than thesecond signal input to the second signal input port; wherein thecomparison signal has a second logic level when the first signal inputto the first signal input port is greater than the second signal inputto the second signal port; and, wherein each of the first input signaland the second input signal comprises more bits than the comparisonsignal.
 2. The semiconductor device according to claim 1, wherein theselection signal generation circuit is configured to, when the firstinput signal includes first to N{circumflex over ( )}th bits, the secondinput signal includes first to N{circumflex over ( )}th bits, theselection signal includes first to (N−1){circumflex over ( )}th bits,and N is set to a natural number of 2 or more, generate the(N−1){circumflex over ( )}th bit of the selection signal by comparingthe N{circumflex over ( )}th bit of the first input signal and theN{circumflex over ( )}th bit of the second input signal.
 3. Thesemiconductor device according to claim 1, wherein the selection signalgeneration circuit is configured to, when the first input signalincludes first to N{circumflex over ( )}th bits, the second input signalincludes first to N{circumflex over ( )}th bits, the selection signalincludes first to (N−1){circumflex over ( )}th bits, and N is set to anatural number of 2 or more, generate the (N−1){circumflex over ( )}thbit of the selection signal which has a first logic level, when theN{circumflex over ( )}th bit of the first input signal is different fromthe N{circumflex over ( )}th bit of the second input signal, andgenerate the (N−1){circumflex over ( )}th bit of the selection signalwhich has a second logic level, when the N{circumflex over ( )}th bit ofthe first input signal is the same as the N{circumflex over ( )}th bitof the second input signal.
 4. The semiconductor device according toclaim 3, wherein the comparison signal generation circuit is configuredto output the N{circumflex over ( )}th bit of the first input signal asthe comparison signal when the (N−1){circumflex over ( )}th bit of theselection signal has the first logic level.
 5. The semiconductor deviceaccording to claim 3, wherein the comparison signal generation circuitis configured to output a signal obtained by inverting and buffering theN{circumflex over ( )}th bit of the second input signal as thecomparison signal when the (N−1){circumflex over ( )}th bit of theselection signal has the first logic level.
 6. The semiconductor deviceaccording to claim 3, wherein the comparison signal generation circuitis configured to generate the comparison signal by comparing the firstbit of the first input signal and the first bit of the second inputsignal when all of the first to (N−1){circumflex over ( )}th bits of theselection signal are set to the second logic level.
 7. The semiconductordevice according to claim 3, wherein the comparison signal generationcircuit is configured to generate the comparison signal which has thesecond logic level, when all of the first to (N−1){circumflex over( )}th bits of the selection signal are set to the second logic level,the first bit of the first input signal has the second logic level, andthe first bit of the second input signal has the first logic level. 8.The semiconductor device according to claim 3, wherein the comparisonsignal generation circuit is configured to generate the comparisonsignal which has the first logic level, when all of the first to(N−1){circumflex over ( )}th bits of the selection signal are set to thesecond logic level and the first bit of the first input signal has thefirst logic level.
 9. The semiconductor device according to claim 1,wherein the comparison signal comprises one bit.
 10. A semiconductordevice comprising: a selection signal generation circuit configured togenerate an (N−1){circumflex over ( )}th bit of a selection signal whichhas a first logic level, when an N{circumflex over ( )}th bit of a firstinput signal is different from an N{circumflex over ( )}th bit of asecond input signal; and a comparison signal generation circuitconfigured to receive first and second input signals and configured tooutput the N{circumflex over ( )}th bit of the first input signal as acomparison signal when the (N−1){circumflex over ( )}th bit of theselection signal has the first logic level, wherein N is a naturalnumber of 2 or more, the comparison signal generation circuit comprisinga plurality of serially-connected code selection circuits, each codeselection circuit having: first and second input signal ports, aselection signal port and an output port from which the comparisonsignal is output responsive to the value of a signal provided to theselection signal port; wherein the comparison signal has a first logiclevel when the first input signal is set to be equal to or smaller thanthe second input signal, wherein the comparison signal has a secondlogic level when the first input signal is set to be larger than thesecond input signal, and wherein each of the first input signal and thesecond input signal comprises more bits than the comparison signal. 11.The semiconductor device according to claim 10, wherein the selectionsignal generation circuit is configured to generate the (N−1){circumflexover ( )}th bit of the selection signal which has a second logic level,when the N{circumflex over ( )}th bit of the first input signal is thesame as the N{circumflex over ( )}th bit of the second input signal. 12.The semiconductor device according to claim 11, wherein the comparisonsignal generation circuit is configured to generate the comparisonsignal by comparing a first bit of the first input signal and a firstbit of the second input signal when all bits included in the selectionsignal are set to the second logic level.
 13. The semiconductor deviceaccording to claim 11, wherein the comparison signal generation circuitis configured to generate the comparison signal which has the secondlogic level, when all the bits included in the selection signal are setto the second logic level, the first bit of the first input signal hasthe second logic level, and the first bit of the second input signal hasthe first logic level.
 14. The semiconductor device according to claim11, wherein the comparison signal generation circuit is configured togenerate the comparison signal which has the first logic level, when allthe bits included in the selection signal are set to the second logiclevel and the first bit of the first input signal has the first logiclevel.
 15. A semiconductor device comprising: a selection signalgeneration circuit configured to generate an (N−1){circumflex over( )}th bit of a selection signal which has a first logic level, when anN{circumflex over ( )}th bit of a first input signal is different froman N{circumflex over ( )}th bit of a second input signal; and acomparison signal generation circuit configured to receive first andsecond input signals and which is configured to output a comparisonsignal by inverting and buffering the N{circumflex over ( )}th bit ofthe second input signal when the (N−1){circumflex over ( )}th bit of theselection signal has the first logic level, wherein N is a naturalnumber of 2 or more, the comparison signal generation circuit comprisinga plurality of serially-connected code selection circuits, each codeselection circuit having: first and second input signal ports, aselection signal port and an output port from which the comparisonsignal is output responsive to the value of a signal provided to theselection signal port; wherein the comparison signal has a first logiclevel when the first input signal is set to be equal to or smaller thanthe second input signal, wherein the comparison signal has a secondlogic level when the first input signal is set to be larger than thesecond input signal, and wherein each of the first input signal and thesecond input signal comprises more bits than the comparison signal. 16.The semiconductor device according to claim 15, wherein the selectionsignal generation circuit is configured to generate the (N−1){circumflexover ( )}th bit of the selection signal which has a second logic level,when the N{circumflex over ( )}th bit of the first input signal is thesame as the N{circumflex over ( )}th bit of the second input signal. 17.The semiconductor device according to claim 16, wherein the comparisonsignal generation circuit is configured to generate the comparisonsignal by comparing a first bit of the first input signal and a firstbit of the second input signal when all bits included in the selectionsignal are set to the second logic level.
 18. The semiconductor deviceaccording to claim 16, wherein the comparison signal generation circuitis configured to generate the comparison signal which has the secondlogic level, when all the bits included in the selection signal are setto the second logic level, the first bit of the first input signal hasthe second logic level, and the first bit of the second input signal hasthe first logic level.
 19. The semiconductor device according to claim16, wherein the comparison signal generation circuit is configured togenerate the comparison signal which has the first logic level, when allthe bits included in the selection signal are set to the second logiclevel and the first bit of the first input signal has the first logiclevel.